SoC, ASIC, FPGA designs for AI/ML, data processing, control, and communications

-Instrumentation and Control for a Neutron-Flux Detector sub-system : design of solid-state relays (break-before-make) controllers and robust signal processing/communications links to a central master controller unit. Control and monitoring of Calibration, Run, I-V, and self-test modes of the detectors. Reconfigurable sequencer (design and implementation) for auto-sampling of multiple ADC channels. Altera Cyclone-V and Quartus (Qsys, PlatformDesigner). Avalon/AXI4-Stream implementations

• Avionics FPGA and ASIC systems for next generation avionics and GPS receivers. L1 C/A channel processing and Gold code and carrier measurements and optimizations . L2 CM/CL channel processing, CM/CL local code generation and zero-padding for code dispreading of the received stream.
• Versal-ACAP processors for high speed, high bandwidth sensor/detector arrays and RFIC applications. Completed a custom SystemVerilog architecture for ARM AXI4-Stream data link processing for Aurora 64b/66b multi-Gigabit Serdes optical transceiver links
• Completed ASIC Arbiter modules Formal verification with System Verilog Assertions (SVAs, classes, coverage, constraints ) in Cadence Jasper and in Synopsys VCFormal. • Completed Ph.D. level research in 128-way VLIW SIMD micro-architecture for DNN inference acceleration with HBM2 sub-system interface. An ISA instruction-extension can be used to control the accelerator. • Completed Ph.D. level research in a novel conditional branch predictor micro-architecture, using a Perceptron and 128-bit History Buffer. Gem5 architectural simulations show better or equal branch prediction performance than a standard GSHARE branch predictor. • Completed Ph.D. level research in ASIC std cell flows, Cadence Innovus clock net routing, std cell place&route flows (row-based, or custom-keep-out obstacles based); work examples on Github :
• FPGA designs for medical CT, PET, and MRI scanners. High speed PCIe-based DMA channel architectures for data acquisition and data processing for medical scanner subsystems. • Defined and implemented the FPGA-side of several product features, including : • C/C++ HLS signal processing modules and implemented as signed fixed-point arithmetic with Vitis - Vivado for Ultrascale+ FPGAs. Applications to RF and Magnetic field sensing and control (MRI). • Power Amplifier (PA) control+status interfaces over multiplexed data and address PA bus (MRI)
• Start/stop scan control logic (pre-scan calibration) for scan preparation and configuration. • PCIe Gen3 x 8 endpoints with support for XDMA transfers to/from on-FPGA SRAM and to/from off-FPGA DRAM, under transfer constraints such as bandwidth, latency, and jitter. • Versal-ACAP Ethernet MRMAC node with packet generator for link loop-back testing. • Versal-ACAP AI-Engine DSP filters mapped with Model-Composer for parallel processing in a 7-way VLIW SIMD architecture. • Completed ASIC Arbiter modules Formal verification with System Verilog Assertions (SVAs, classes, coverage, constraints, interfaces) in Cadence Jasper and in Synopsys VCFormal.
• Design and integration of a novel streaming LDPC encoder interface block for a 4G/5G (600,900) code with Zc=60. The interface is low-latency ( approx. 80 cycles ) between 16- bit wide SRAM and 600 bits at the encoder input bus. The same interface block is reconfigured to connect the encoder output (900 bits ) to 16-bit SRAM. • Contributed interface designs for a first successful LDPC link in a Canopy fixed wireless network.