Design projects with Industrial groups at GE-Nuclear-Power, Appareo-Aviation, Lockheed-Martin, Canon-Medical, Cambium-Networks, L3-Harris
- Instrumentation and Control for a Neutron-Flux Detector sub-system : design of solid-state relays (break-before-make) controllers and robust signal processing/communications links to a central master controller unit. Control and monitoring of Calibration, Run, I-V, and self-test modes of the detectors. Reconfigurable sequencer (design and implementation) for auto-sampling of multiple ADC channels. Altera Cyclone-V and Quartus (Qsys, PlatformDesigner, SystemConsole). Avalon/AXI4-Stream implementations.
- Avionics FPGA and ASIC systems for next generation avionics and GPS receivers. L1 C/A channel processing and Gold code and carrier measurements and optimizations . L2 CM/CL channel processing, CM/CL local code generation and zero-padding for code dispreading of the received stream
- Versal-ACAP FPGA processors for high speed, high bandwidth sensor/detector arrays and RFIC applications. Completed a custom SystemVerilog architecture for ARM AXI4-Stream data link processing for Aurora 64b/66b multi-Gigabit Serdes optical transceiver links. Completed ASIC Arbiter modules Formal verification with System Verilog Assertions (SVAs, classes, coverage, constraints, interfaces) in Cadence Jasper and in Synopsys VC- Formal. • Completed Ph.D. level research in 128-way VLIW SIMD micro-architecture for DNN inference acceleration with HBM2 sub-system interface. An ISA instruction-extension can be used to control the accelerator. The accelerator can be added to a Tomasulo Out-of-Order-execution in-order completion pipeline. Completed Ph.D. level research in a novel conditional branch predictor micro-architecture, using a Perceptron and 128-bit History Buffer. Gem5 architectural simulations show better or equal branch prediction performance than a standard GSHARE branch predictor. • Ph.D. level research in ASIC std cell flows, Cadence Innovus clock net routing, std cell place&route flows (row-based, or custom-keep-out obstacles based); work examples on Github : Completed research in ASIC standard cell flow (CMOS gsclk45 Cadence process) for Random-Number generator, example on https://github.com/niliev4/rng_self_calib Completed research in ASIC standard cell flow for a low-power 4-bit ALU in FDSOI process, full schematics to layout (DRC, LVS, RC-extract, post-layout sim) flow. Completed research in analog circuits for ASIC cell flow (CMOS gpdk180 Cadence process) spiking neuron-synapse, in ADE-XL Spectre/HSpice Monte-Carlo simulator; work examples on Github: https://github.com/niliev4/Spiking_Neural_Synapse_CMOS180 Completed research in analog circuits for ASIC mixed-signal cell flow (CMOS gpdk45 Cadence process), cell for 2D/3D linear system solvers; Synopsys HSpice; work examples on Github: https://github.com/niliev4/Analog-CMOS-Systems-and-circuits-for-2D-3D-Localization/blob/main/Analog_CMOS_systems_for_2D_3D_Localization_N_Iliev_UIC%20_Tech_Report.doc FPGA designs for medical CT, PET, and MRI scanners. High speed PCIe-based DMA channel architectures for data acquisition and data processing for medical scanner sub-systems. C/C++ HLS signal processing modules and implemented as signed fixed-point arithmetic with Vitis - Vivado for Ultrascale+ FPGAs. Applications to RF and Magnetic field sensing and control (MRI). ARM GIC (Zynq MPSoC) interrupt controller interfaces for various interrupt sources (sensors) with multiple sample rates (MRI, CT, others). Power Amplifier (PA) control+status interfaces over multiplexed data and address PA bus (MRI).
About University of Illinois Chicago
UIC researchers are advancing discoveries across the life sciences, engineering, computer science, energy, manufacturing, public health, biomedical and other fields. Our scientists are supported by funding from the National Institutes of Health, National Science Foundation, U.S. Department of Energy, and other federal agencies.
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