Hardware Security Assessment: Side Channels, Secure Processors, Trusted Execution, FPGAs, and Connected Devices

Many of the most serious security failures happen below the software layer, where standard penetration tests and code reviews don’t look. Side-channel attacks through caches, timing, power, and shared hardware can leak keys and sensitive data. Trusted execution environments and confidential computing features are often misconfigured or misunderstood. FPGAs deployed in products or in the cloud introduce their own attack surfaces, and connected lab instruments, medical devices, and IoT products are increasingly targeted at the hardware level. This service provides an independent, expert review of the hardware security of your products and infrastructure. Depending on your needs, I can review processor and SoC security architectures, evaluate side-channel and covert-channel risks, and assess your use of trusted execution environments and confidential computing. I can also review FPGA designs and cloud FPGA deployments, evaluate device identity, authentication, and anti-counterfeiting approaches, including physically unclonable functions (PUFs), and review security verification practices for hardware designs. Deliverables include a threat model, a written assessment with prioritized findings and recommended mitigations, and a technical readout for your engineering and security teams. I can also advise early in the design process, when security features are cheapest to add. Engagements are remote-first with optional on-site sessions in the Chicago area, begin with a free 30-minute discovery call, and are covered by NDA. A focused design review typically takes [2–4] weeks, and a broader product or architecture assessment takes [6–10] weeks depending on scope. Ongoing advisory retainers are available. I take on [1–2] engagements at a time. This is a strong fit for semiconductor and SoC companies, FPGA users, cloud and data-center hardware teams, makers of medical devices, lab instruments, and IoT products, and companies adopting confidential computing to protect sensitive R&D data. I am an Associate Professor of Electrical and Computer Engineering at Northwestern University, where I lead the Computer Architecture and Security Lab (CASLAB). I am the author of “Principles of Secure Processor Architecture Design,” covering trusted execution environments and side-channel threats and protections, and co-editor of “Security of FPGA-Accelerated Cloud Computing Environments.” My research spans secure processor architectures, security verification of hardware, cloud FPGA attacks and defenses, side and covert channels, and DRAM-based PUFs. I hold a PhD from Princeton, am an NSF CAREER award recipient, and am a Senior Member of the IEEE and ACM.