Post-Quantum Cryptography in Hardware: Implementation, Optimization & Side-Channel Review for Chips, FPGAs, and Embedded Devices

Moving to post-quantum cryptography is hardest where cryptography runs in hardware. The new NIST algorithms (ML-KEM, ML-DSA, SLH-DSA, and HQC) have much larger keys and signatures and very different computational profiles than RSA and elliptic-curve cryptography. That strains area, memory, power, and latency budgets on chips, FPGAs, secure elements, and constrained devices. Implementations that are functionally correct can still leak secret keys through timing, power, or electromagnetic side channels. This service helps hardware and embedded teams get post-quantum cryptography right the first time. I can review your target platform and requirements and recommend algorithms and parameter sets. I can also design or evaluate hardware accelerators and hardware/software co-designs, benchmark performance and resource use, and assess implementations for constant-time behavior and side-channel resistance. Deliverables can include an architecture recommendation, a written design or security review with prioritized findings, performance comparisons, and guidance on hybrid classical/post-quantum modes and crypto-agility so devices in the field can be updated as standards change. For teams building from scratch, I can advise on reference designs, including open-source hardware my group has published, and support verification and test planning. Engagements are remote-first with optional on-site sessions in the Chicago area, begin with a free 30-minute discovery call, and work under NDA. A focused design or code review typically takes [2–4] weeks. Architecture and accelerator design advisory runs [6–12] weeks depending on scope, and ongoing advisory retainers are available. I take on [1–2] engagements at a time. This is a strong fit for semiconductor and FPGA companies, makers of medical devices, industrial controllers, automotive and IoT products, secure element and HSM vendors, and any company whose products have long field lifetimes and need to stay secure into the 2030s. I am an Associate Professor of Electrical and Computer Engineering at Northwestern University, where I lead the Computer Architecture and Security Lab (CASLAB). My group has built hardware accelerators for code-based, hash-based, and signature-based post-quantum algorithms, including fast and efficient hardware implementation of HQC. I am part of the Classic McEliece team in NIST’s post-quantum standardization process and collaborate with SandboxAQ on hardware implementations of post-quantum digital signatures. I hold a PhD from Princeton and am an NSF CAREER award recipient.